Your Partner in Design Services

Space

• Space Edge Processor – Schematic design of a motherboard with a CPU/GPU and two Versals (Ethernet Switch and Coprocessor). FPGA design for hardware testing.  FPGA design for support of CPU/GPU. FPGA design of a Layer 2 Ethernet Switch.

 

• Space Regenerative Processor – System design contributor (backplane-balsed system with six unique plug in boards).  Schematic design of dual Ultrascale+ (Zynq and Virtex) board.  FPGA design for hardware testing. FPGA design for switch logic.  (System included one of hte optical modems referenced in the next bullet).

 

• Free Space Optical Modems – Schematic design of three Ultrascale+ / Modem ASIC boards.  Oversaw subsequent schematic design of a Versal / Modem ASIC board.  FPGA design or hardware testing on all four boards.  FPGA design for control of Modem ASIC, lasers, CDM, uICR, and TECs.

 

• Spaceflight Integrated Vehicle Fluids – FPGA design of a redundant communication system spread across a network of SmartFusion2 devices.  FPGA design for hardware testing.

• Camera-guided Moon Lander - FPGA design of video processing system in a Zynq-7000 for the output of a CMOS Image Sensor.

• Moon Rover - Mentored a junior engineer through the FPGA design of glue logic in a ProASIC3.

 

• Satellite Camera – Mentored a junior engineer through the schematic design of a camera board with 4K imager and Ultrascale FPGA.  FPGA design of housekeeping logic on the camera board.  FPGA design of image-rendering logic for testing.

 

• FOC Motor Control on Telecommunications Satellite – Schematic design of two DSP / ProASIC3 co-processing boards.  FPGA design for hardware testing.  FPGA design for FOC motor control.

Electronic Design Automation (EDA)

• ASIC Emulator - Schematic design of an ATCA Card with six Arria-10 devices and a Cyclone-V to be used in a fourteen slot chassis for ASIC emulation.  FPGA design for hardware testing.  FPGA design Cyclone-V control of Arria-10 devices.

 

• Hardware Accelerated Simulator - Schematic design of a Stratix-V and Cyclone-V SOC PCIe Card for hardware accelerated RTL simulation.  FPGA design for hardware testing.  FPGA design for traffic management in Cyclone-V SOC.